library ieee;
use ieee.std_logic_1164.all;

entity hazard is
  port (
    exMemRead   : in std_logic;
    
    exRt, dRs, dRt  : in std_logic_vector(4 downto 0);
    
    pcen, ifen, Hazard      : out std_logic

  );
end hazard;

architecture behavioral of hazard is
  signal stall : std_logic;

begin
            
  stall  <= '1' when exMemRead = '1' and (((dRs xnor exRt) = "11111") or ((dRt xnor exRt) = "11111")) else
            '0';

  pcen <= '0' when stall = '1' else
          '1';
  ifen <= '0' when stall = '1' else
          '1';

  Hazard <= stall;
  
end behavioral;